1. Field of the Invention
The present invention relates to a bus apparatus. More particularly, the present invention relates to a bus apparatus supporting default speculative bus transactions and non-speculative (NS) extension.
2. Description of the Related Art
A bus transaction is a transaction flown from a bus master to a bus slave to carry data from master to slave (a write transaction), or to inquire data back to a master from a slave (a read transaction). The bus master is usually a data processing engine (DPE) such as a microprocessor that fetches, decodes, and executes instructions. The bus slave is usually a storage device such as a physical memory. Since the processing throughput of a DPE is never high enough, many pipelined DPEs support speculative instruction fetching for higher throughput. When such a DPE fetches a branch instruction, the DPE predicts a target address of the branch instruction and then fetches instructions at the target address to feed the pipeline instead of idly waiting for the confirmation of the target address. When the DPE finds out the prediction is incorrect later, the DPE simply flushes its pipeline to get rid of the mis-fetched instructions. When the prediction is correct, the DPE saves time because the instructions are already in the pipeline. Similarly, there are speculative bus transactions for speeding up a bus system.
A bus master may have multiple bus interfaces connecting to different peripheral devices, i.e., bus slaves. Each bus interface may be mapped to a different address space. For such a bus master, there are three conditions for committing an instruction to issue a corresponding bus transaction. The first condition is the execution of the instruction, which means the instruction is not flushed or cancelled. The second condition is the completion of the translation from the address of the instruction to the address space corresponding to one of the bus interfaces. The third condition is the permissions at the address of the instruction allow the access of the instruction. In a non-speculative bus system, a bus master sends a transaction to a bus slave only when the aforementioned three conditions for the corresponding instruction are all satisfied.
On the other hand, in a speculative bus system, a bus master may send a transaction to a bus slave before fully satisfying the aforementioned three conditions as long as the bus master somehow predicts or guesses that the instruction is likely to be committed to generate the aforementioned bus transaction to the bus slave. Such bus transactions are speculative bus transactions. When the bus master finds out later that the instruction is to be aborted, the corresponding speculative bus transaction is also aborted by discarding the data to be written to the bus slave or the data read from the bus slave. When the instruction is to be committed, a speculative bus transaction is always faster than a non-speculative bus transaction because the speculative bus transaction is issued earlier.